Optical Spinal Implant (OSI) Project – Two Tracks: Biomedical Integrated Circuits and Embedded Artificial Intelligence

Description

The sBioM laboratory at Université Laval, led by Professor Benoit Gosselin, is recruiting a PhD student to contribute to the Optical Spinal Implant (OSI) project. The project brings together specialists in microelectronics, neuroscience, optogenetics, wireless systems and preclinical validation, as well as industry and clinical partners.

The OSI project aims to develop a miniaturized optical spinal implant combining optogenetic stimulation, fluorescence sensing, on-board processing and wireless communication. This closed-loop neuromodulation platform is intended to precisely target circuits associated with neuropathic and nociceptive pain while meeting stringent requirements for power consumption, size, safety and biocompatibility.

The successful candidate will contribute to the OSI's core microelectronic system through one of two complementary tracks: (1) ultra-low-power biomedical integrated circuit design or (2) embedded artificial intelligence and TinyML algorithm development for sensing and closed-loop control. Strong expertise in either track is sufficient to apply; the research will be conducted in collaboration with specialists in the other track.

**Research Scope and Objectives**

Microelectronics/ASIC track: design ultra-low-power application-specific integrated circuits to drive optical stimulation, acquire weak fluorescence signals, and integrate processing, communication and power supply functions. Embedded AI/TinyML track: develop, compile (or synthesize) and deploy algorithms capable of detecting pain states and adapting stimulation in real time under tight memory, computational, energy and latency constraints. Depending on the candidate's interests, the research may also explore inductive, capacitive, ultrasonic or hybrid wireless power transfer (WPT) architectures.

**Examples of Research Projects and Tasks**

- Microelectronics/ASIC track: define the circuit architecture and design analog, mixed-signal or digital blocks for optical stimulation, photodiode readout, signal conditioning and ultra-low-power processing.
- Embedded AI/TinyML track: prepare data, develop and evaluate lightweight models, then quantize, compile (or synthesize) and deploy them on a microcontroller or hardware accelerator for adaptive pain-state detection and closed-loop control. Ultimately, the algorithms will run on an ASIC.
- Contribute to system validation: hardware-algorithm co-simulation, verification, tape-out or characterization, depending on the candidate's background, followed by integration with the interposer, flexible circuit, LEDs, photodiodes and UWB link; as needed, prototype and evaluate inductive, capacitive, ultrasonic or other WPT solutions.

**A Typical Day or Week**

Depending on the chosen track, a typical week will include circuit design and simulation or TinyML model development and optimization, scripting and testbench development, prototype characterization, data analysis, scientific documentation and interdisciplinary meetings. The successful candidate will collaborate with the microelectronics, AI, neuroscience, RF and microsystems teams, as well as project partners.

Requirements and Conditions

Essential Qualifications
- A master's degree in electrical engineering, microelectronics, computer engineering, artificial intelligence or a closely related field, completed or nearing completion.
- Demonstrated expertise in at least one of the two tracks: (1) design, simulation or verification of analog, mixed-signal or digital CMOS integrated circuits; or (2) machine learning, signal processing and model deployment on embedded platforms.
- Ability to program and analyze results, communicate clearly, document research and collaborate within an interdisciplinary team.

Additional Assets
- For the ASIC track: experience with microelectronic CAD tools, an ASIC design flow, circuit characterization or photodiode interfaces. For the TinyML track: experience with Python and a machine learning framework, as well as quantization, compression, code generation or deployment on a microcontroller, FPGA or hardware accelerator.

Application Deadline

November 14, 2026